Clock frequency requirements of electronics systems are continually increasing. Thus, systems designers must address increasingly complex clock synchronization requirements. For example, in a system which uses application specific integrated circuits (ASICs), it is important to minimize on-chip clock distribution delay and total system clock skew in order to provide safe data transfer between the ASICs. The need for effective high frequency clock synchronization is therefore great.
A conventional approach to the problem of clock skew minimization provides a digital phase locked loop (PLL) 10 as shown in FIG. 1 for each IC in the system. Each PLL 10 attempts to eliminate the effects of the on-chip clock distribution delay of the associated IC and typically includes a phase detector 12 and a digital delay line or adjust circuitry 14, each of which has the reference clock CLKR as an input. Adjust circuitry 14 is arranged as a component of the internal clock CLKI distribution path. Internal clock CLKI is fed back as an input to phase detector 12. Phase detector 12 detects information about the phase relationship between reference clock CLKR and internal clock CLKI, and provides this information to adjust circuitry 14. Adjust circuitry 14 adjusts the delay of internal clock CLKI distribution path based on the phase information provided by phase detector 12. This feedback adjustment of internal clock CLKI distribution path delay is continued until internal clock CLKI and reference clock CLKR are acceptably synchronized.
Conventional PLL 10 exhibits an undesirable large phase jitter. Phase jitter is a function of the phase resolution of the phase detector and the step size of adjust circuitry 14. Another limitation of PLL 10 is that if a phase lock condition is not achieved due to various system conditions a failure will occur, however, PLL 10 cannot identify whether a failure has occurred. Therefore the PLL does not provide the synchronization between ASICs during this failure mode. Only a manual reset of PLL 10 will fix this problem.
It is an object of this invention to provide a PLL that provides an improvement in phase jitter resolution over prior art PLL 10. It is another object of this invention to provide a PLL that monitors itself and identifies PLL locking failures and takes appropriate action to address the failure. Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings herein.